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Setups

Due to our diverse lab equipment, we are running various setups of solvers. Each single FPGA device hosts several solver instances, which we call slices. Some of the FPGA setups are represented by only a single available board.

FPGASlicesClock FreqSEBoardsTotal
Sum2470
Altera Stratix EP1S80 74120 MHz 88.8188
Stratix II EP2SGX9077180 MHz138.61138
Xilinx Spartan-3 XC3S1000 15 92 MHz 13.84 55
Spartan-3E XC3S500E 9100 MHz 9.02 18
Virtex-2 XC2VP30 29146 MHz 42.31 42
Virtex-4 XC4VFX12 10153 MHz 15.31 15
Virtex-4 XC4VLX200 142126 MHz178.92 357
Virtex-4 XC4VLX160 125143 MHz178.781430
Virtex-5 XC5VLX50T 33163 MHz 53.85 269
Virtex-5 XC5VSX50T 36161 MHz 58.01 58
SE
Slice Equivalent measured in the number of 100 MHz Slices of the same computational power.

The clock frequencies might appear forbiddingly low as compared to the multi-gigahertz general purpose CPUs. The power of our designated design is the avoidance of any instruction set overhead and the tremendous concurrency even on a single chip.

As we can only utilize the idle time of these of our lab resources, we are constantly searching for sponsors of high-performance FPGAs.

Sponsors
Signalion
Contact

Prof. Rainer G. Spallek
rainer.spallek@tu-dresden.de

Thomas B. Preußer
thomas.preusser@tu-dresden.de

Bernd Nägel
bernd.naegel@mailbox.tu-dresden.de

Telefax
+49 (0)351 463 38324
Street Address
Nöthnitzer Straße 46, Room 1095
01187 Dresden
Mail Address
Chair for VLSI – EDA
Fakultät Informatik
Technische Universität Dresden
D-01062 Dresden